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d a t a sh eet preliminary speci?cation supersedes data of 1999 jun 28 file under integrated circuits, ic22 2000 jan 27 integrated circuits SAA8115HL digital camera usb interface
2000 jan 27 2 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL contents 1 features 2 applications 3 general description 4 ordering information 5 quick reference data 6 block diagram 7 pinning 8 functional description 8.1 video synchronization 8.2 frame rate converter and sdram interface 8.3 video formatter: downsampler and cutter 8.4 compression engine 8.5 transfer buffer 8.6 usb video fifo 8.7 psie-mmu, i 2 c-bus interface and usb ram space 8.8 atx interface 8.9 audio 8.10 sensor pulse pattern generator 8.11 power management 8.12 power supply 9 control register description 9.1 snert (uart) 9.2 i 2 c-bus interface 10 limiting values 11 thermal characteristics 12 operating characteristics 13 timing 14 application information 15 package outline 16 soldering 16.1 introduction to soldering surface mount packages 16.2 reflow soldering 16.3 wave soldering 16.4 manual soldering 16.5 suitability of surface mount ic packages for wave and reflow soldering methods 17 definitions 18 life support applications 19 purchase of philips i 2 c components
2000 jan 27 3 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL 1 features vga (progressive mode), cif and medium resolution (pal non-interlaced mode) ccd sensors compliant d1 digital video input (8 bits yuv 4:2:2 time multiplexed) internal pulse pattern generator (ppg) dedicated for vga panasonic, cif and medium resolution sharp sensors or compatibles, and frame rate selection frame rate converter sdram interface for high quality vga snapshot (uncompressed 4:2:2 or 4:2:0) downsampler and scaler (programmable formatter for cif, qcif, sub-qcif, sif and qsif) controlled via snert (uart) interface flexible compression engine controlled via snert (uart) interface selectable output frame rate (up to 15 fps in vga, up to 30 fps in cif and qcif) video packetizer fifo i 2 c-bus interface for communication between the usb protocol hardware and the external microcontroller microphone/audio input to usb (microphone supply, controllable gain and adc) integrated analog bus driver (atx) integrated main oscillator integrated 5 v power supply and reset circuit including functionalities for bus-powered usb device programmable (frequency and duty cycle) switch mode power signal for ccd supply miscellaneous functions (e.g. power management, pll for audio frequencies). 2 applications low-cost desktop video applications with usb interface. 3 general description the SAA8115HL is the second generation of integrated circuit applicable in pc video cameras to convert d1 video signals and analog audio signals to properly formatted usb packets. this powerful successor of the saa8117hl can handle up to 15 fps in vga format or 30 fps in cif format. high snapshot quality is achievable using the sdram interface to an external memory. it is designed as a back-end of the saa8112hl (general camera digital processing ic) and is optimized for use with the tda8784 to tda8787 (camera pre-processing ics).
2000 jan 27 4 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL 4 ordering information 5 quick reference data measured over full voltage and temperature range note 1. this concerns pins vbus1 and vbus2. type number package name description version SAA8115HL lqfp144 plastic low pro?le quad ?at package; 144 leads; body 20 20 1.4 mm sot486-1 symbol parameter conditions min. typ. max. unit v ddd digital supply voltage 3.0 3.3 3.6 v v dda analog supply voltage 3.0 3.3 3.6 v v dda_usb analog supply voltage from usb note 1 4.0 5.0 5.5 v i dd(tot) total supply current v ddd = 3.3 v -- tbf ma v i input signal levels 3. 0v 2000 jan 27 5 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 6 block diagram ha ndbook, full pagewidth fce349 compression engine video formatter frame rate converter snert interface yuv7 to yuv0 llc vs href transfer buffer usb video fifo psie mmu audio adc audio pll i 2 c-bus interface atx usb ram space power management ucpor ucint ucclk 104 99 atxdm atxdp 81 80 sda scl 107 106 32 31 30 snda snres sncl 36 35 34 sdram interface ad10 to ad0 dq15 to dq0 77, 76, 75, 74, 67, 65, 62, 60, 61, 63, 64, 66, 70, 71, 72, 73 48, 47, 45, 44, 42, 39, 38, 40, 41, 43, 46 28, 27, 26, 25 22, 21, 20, 19 audio variable gain amplifier vgain 130 audio low noise amplifier lnaout 131 micin 132 microphone supply micsupply 133 main oscillator xout 121 xin 120 casb 56 rasb 52 sdclk 58 web 57 clken 55 csb 51 dqm 59 m3 to m0 115, 116, 117, 118 reset 33 suspend clockon 100 109 trc 112 snapshot 110 suspreadynot 111 smp 108 genpor 103 v ddd1 to v ddd3 24, 53, 102 v dd1 to v dd6 7, 16, 37, 50, 69, 141 v dda1 to v dda6 82, 84, 85, 122, 124, 125 dgnd1 to dgnd4 23, 29, 54, 101 agnd1 to agnd6 79, 88, 93, 119, 123, 134 gnd1 to gnd7 6, 18, 49, 68, 78, 98, 142 reserved1 to reserved6 83, 86, 89, 96, 97, 129 ref1 to ref3 126, 127, 128 dc-to-dc converter off 114 por 113 switched5v 95 lxup 94 lxdown 92 vbus2 91 vbus1 90 3v3 87 pulse pattern generator (ppg) clk2 17 clk1 11 hd 15 vd 14 bcp 13 dcp 12 fcds 10 fs 9 shutter 5 rg 8 c1 to c4 3, 2, 1, 4 a1 to a4 139, 140, 143, 144 b1 to b4 137, 138, 136, 135 105 SAA8115HL fig.1 block diagram.
2000 jan 27 6 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL 7 pinning symbol pin type (1) description c3 1 o horizontal ccd transfer pulse output c2 2 o horizontal ccd transfer pulse output (fh1) c1 3 o horizontal ccd transfer pulse output (fh2) c4 4 o horizontal ccd transfer pulse output shutter 5 o shutter control output for ccd charge reset gnd1 6 p ground 1 for output buffers v dd1 7 p supply voltage 1 for output buffers rg 8 o reset output for ccd output ampli?er gate fs 9 o data sample-and-hold pulse output to tda8784/87 (shd) fcds 10 o preset sample-and-hold pulse output to tda8784/87 (shp) clk1 11 o pixel clock to tda8784/87 and saa8112hl dcp 12 o dummy clamp pulse output to tda8784/87 bcp 13 o optical black clamp pulse output to tda8784/87 vd 14 o vertical de?nition pulse to saa8112hl hd 15 o horizontal de?nition pulse to saa8112hl v dd2 16 p supply voltage 2 for output buffers clk2 17 o double pixel clock to saa8112hl gnd2 18 p ground 2 for output buffers yuv0 19 i multiplexed yuv bit 0 yuv1 20 i multiplexed yuv bit 1 yuv2 21 i multiplexed yuv bit 2 yuv3 22 i multiplexed yuv bit 3 dgnd1 23 p digital ground 1 for input buffers, predrivers and for the digital core v ddd1 24 p digital supply voltage 1 for input buffers, predrivers and one part of the digital core yuv4 25 i multiplexed yuv bit 4 yuv5 26 i multiplexed yuv bit 5 yuv6 27 i multiplexed yuv bit 6 yuv7 28 i multiplexed yuv bit 7 dgnd2 29 p digital ground 2 for input buffers, predrivers and for the digital core llc 30 i line-locked clock input (delayed clk2) for yuv-port from saa8112hl href 31 i horizontal reference input for yuv-port from saa8112hl vs 32 i vertical synchronization input for yuv-port from saa8112hl reset 33 i power-on reset input (for video processing and ppg) snda 34 i/o data input/output for snert-interface (communication between SAA8115HL and saa8112hl) sncl 35 i clock input for snert-interface (communication between SAA8115HL and saa8112hl) snres 36 i reset input for snert-interface (communication between SAA8115HL and saa8112hl)
2000 jan 27 7 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL v dd3 37 p supply voltage 3 for output buffers ad4 38 o sdram output address bit 4 ad5 39 o sdram output address bit 5 ad3 40 o sdram output address bit 3 ad2 41 o sdram output address bit 2 ad6 42 o sdram output address bit 6 ad1 43 o sdram output address bit 1 ad7 44 o sdram output address bit 7 ad8 45 o sdram output address bit 8 ad0 46 o sdram output address bit 0 ad9 47 o sdram output address bit 9 ad10 48 o sdram output address bit 10 gnd3 49 p ground 3 for output buffers v dd4 50 p supply voltage 4 for output buffers csb 51 o sdram chip select output rasb 52 o sdram row address strobe output v ddd2 53 p digital supply voltage 2 for the switchable digital core dgnd3 54 p digital ground 3 for input buffers, predrivers and for the digital core clken 55 o sdram clock enable output casb 56 o sdram column address strobe output web 57 o sdram write enable output sdclk 58 o sdram clock output dqm 59 i/o sdram data mask enable dq8 60 i/o sdram data i/o bit 8 dq7 61 i/o sdram data i/o bit 7 dq9 62 i/o sdram data i/o bit 9 dq6 63 i/o sdram data i/o bit 6 dq5 64 i/o sdram data i/o bit 5 dq10 65 i/o sdram data i/o bit 10 dq4 66 i/o sdram data i/o bit 4 dq11 67 i/o sdram data i/o bit 11 gnd4 68 p ground 4 for output buffers v dd5 69 p supply voltage 5 for output buffers dq3 70 i/o sdram data i/o bit 3 dq2 71 i/o sdram data i/o bit 2 dq1 72 i/o sdram data i/o bit 1 dq0 73 i/o sdram data i/o bit 0 dq12 74 i/o sdram data i/o bit 12 dq13 75 i/o sdram data i/o bit 13 dq14 76 i/o sdram data i/o bit 14 dq15 77 i/o sdram data i/o bit 15 symbol pin type (1) description
2000 jan 27 8 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL gnd5 78 p ground 5 for output buffers agnd1 79 p analog ground 1 for atx (transceiver) atxdp 80 i/o positive driver of the differential data pair input/output (atx) atxdm 81 i/o negative driver of the differential data pair input/output (atx) v dda1 82 p analog supply voltage 1 for atx reserved1 83 - test pin 1 (should not be used) v dda2 84 p analog supply voltage 2 for bandgap (reference) v dda3 85 p analog supply voltage 3 for bandgap, comparator and ring oscillator reserved2 86 - test pin 2 (should not be used) 3v3 87 i 3v3 detector input signal agnd2 88 p analog ground 2 for n-switch reserved3 89 - test pin 3 (should not be used) vbus1 90 i supply voltage input 1 from the usb vbus2 91 i supply voltage input 2 from the usb lxdown 92 o lx coil node output (5 v downconverter) agnd3 93 p analog ground 3 for n-switch lxup 94 i lx coil node input (5 v upconverter) switched5v 95 o 5 v switched power supply reserved4 96 - test pin 4 (should not be used) reserved5 97 - test pin 5 (should not be used) gnd6 98 p ground 6 for output buffers ucint 99 o interrupt output from usb to microcontroller suspend 100 o control output from usb protocol hardware to microcontroller dgnd4 101 p digital ground 4 for input buffers, predrivers and for the digital core v ddd3 102 p digital supply voltage 3 for input buffers, predrivers and one part of the digital core genpor 103 i power-on reset input (for usb protocol hardware) ucpor 104 o control output from usb protocol hardware to microcontroller ucclk 105 o clock output from usb protocol hardware to microcontroller scl 106 i slave i 2 c-bus clock input sda 107 i/o slave i 2 c-bus data input/output smp 108 o switch mode power pulse output for ccd supplies clockon 109 o control output for main oscillator switched on snapshot 110 i input for remote wake-up (snapshot) suspreadynot 111 i input from microcontroller for suspend mode trc 112 i threshold control input for enabling clock por 113 o 3.3 v supply domain ready indicator output off 114 i disable 5 v switchable supply domain input m3 115 i test mode control input signal bit 3 m2 116 i test mode control input signal bit 2 m1 117 i test mode control input signal bit 1 symbol pin type (1) description
2000 jan 27 9 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL note 1. i = input, o = output and p = power supply. m0 118 i test mode control input signal bit 0 agnd4 119 p analog ground 4 for crystal oscillator (48 mhz, 3rd overtone) xin 120 i oscillator input xout 121 o oscillator output v dda4 122 p analog supply voltage 4 for crystal oscillator (48 mhz, 3rd overtone) agnd5 123 p analog ground 5 for pll v dda5 124 p analog supply voltage 5 for pll v dda6 125 p analog supply voltage 6 for ampli?er and adc ref1 126 i reference voltage 1 (used in the adc) ref2 127 i reference voltage 2 (used in the adc) ref3 128 i reference voltage 3 (used in the ampli?er and the adc) reserved6 129 o test pin 6 (should not be used) vgain 130 i variable gain ampli?er input lnaout 131 o low noise ampli?er output micin 132 i microphone input micsupply 133 o microphone supply output agnd6 134 p analog ground 6 for ampli?er and adc b4 135 o vertical ccd load pulse output (vh1x) b3 136 o vertical ccd load pulse output (vh3x) b1 137 o vertical ccd load pulse output b2 138 o vertical ccd load pulse output a1 139 o vertical ccd transfer pulse output (v1x) a2 140 o vertical ccd transfer pulse output (v2x) v dd6 141 p supply voltage 6 for output buffers gnd7 142 p ground 7 for output buffers a3 143 o vertical ccd transfer pulse output (v3x) a4 144 o vertical ccd transfer pulse output (v4x) symbol pin type (1) description
2000 jan 27 10 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL handbook, full pagewidth fce350 SAA8115HL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 c3 c2 c1 c4 shutter gnd1 v dd1 rg fs fcds clk1 dcp bcp vd hd v dd2 clk2 gnd2 yuv0 yuv1 yuv2 yuv3 dgnd1 v ddd1 yuv4 yuv5 yuv6 yuv7 dgnd2 llc href vs reset snda sncl snres smp sda scl ucclk ucpor genpor v ddd3 dgnd4 suspend ucint gnd6 reserved5 reserved4 switched5v lxup agnd3 lxdown vbus2 vbus1 reserved3 agnd2 3v3 reserved2 v dda3 reserved1 v dda2 v dda1 atxdm atxdp agnd1 gnd5 dq15 dq14 dq13 dq12 dq0 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 v dd3 ad4 ad5 ad3 ad2 ad6 ad1 ad7 ad8 ad0 ad9 ad10 gnd3 v dd4 csb rasb v ddd2 dgnd3 clken casb web sdclk dqm dq8 dq7 dq9 dq6 dq5 dq10 dq4 dq11 gnd4 v dd5 dq3 dq2 dq1 a4 a3 gnd7 v dd6 a2 a1 b2 b1 b3 b4 agnd6 micsupply micin lnaout vgain reserved6 ref3 ref2 ref1 v dda6 v dda5 agnd5 v dda4 xout xin agnd4 m0 m1 m2 m3 off por trc suspreadynot snapshot clockon 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 fig.2 pin configuration.
2000 jan 27 11 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL 8 functional description 8.1 video synchronization the video synchronization module is capable of locking to the video signal implementing a horizontal gate signal href (href = high when data is valid) and a vs signal indicating the start of a new video frame. 8.2 frame rate converter and sdram interface an optional sdram (external) can be accessed using the sdram interface which is integrated in the SAA8115HL. pinning and functionality is based on the nec m pd4516161 (16 mbits) and the nec m pd4564163 (64 mbits). when used, the memory is placed at the video input of the SAA8115HL before prefilter, scaler and compression engine. at this point only yuv 4 : 2 : 2 formatted data is available. the use of the sdram is twofold: lowering the frame rate. the memory enables to store one frame of video accumulated at a specific rate and to read it out at a lower frame rate. for interline vga sensors, the input frame rate is either 30 fps or 15 fps. it can be lowered with a factor of 2, 3, 6, 16 or 32. for cif or medium resolution pal, the input frame rate is only 30 fps enhanced snapshot mode. storage of full size vga pictures in 4:2:2 format which can be retrieved upon dedicated software command. 8.3 video formatter: downsampler and cutter this block is used to achieve the required output format from the specified sensor formats (see fig.3). it works for yuv 4 : 2 : 2 only. in raw mode this block is by-passed to create a full resolution snapshot. horizontally a downsampling from 512 or 640 to either 384, 320, 192 or 160 or from 352 to 176 is necessary. the horizontal downsampling is performed with the use of a variable phase delay filter (vpd-4). this filter can realize the needed downsample factors. to avoid aliasing, this module also contains a prefilter which has four modes: no filter for medium resolution pal (512 288) to cif (352 288) or sif (320 240) prefilter a (3 taps) for vga (640 480) to cif or sif, cif to qcif (176 144) or qsif (160 120) prefilter b (7 taps) for medium resolution pal to qcif or qsif prefilter a combined with prefilter b-comb (13 taps) for vga to qcif or qsif. prefilter b-comb is similar to prefilter b but inserts extra taps with amplification 0. the vertical downsampling in pal mode is from cif to qcif only. this is done via a vertical filter a (3 taps). in vga mode a 4 taps polyphase filter is applied to scale from 640 480 to cif and qcif. from a full size qcif picture a sub-qcif (128 96) cut can be made. for the zoomed sub-qcif format, the origin (upper left corner) is programmable via snert in 13 steps (both horizontally and vertically), so that an electronic pan and tilt is possible. the incoming 4:2:2 data is vertically filtered to 4:2:0, in order to be sent over usb, by throwing away colour samples. in the even lines the v-samples are discarded, in the odd lines the u-samples.
2000 jan 27 12 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL 8.4 compression engine the compression engine module (see fig.3) can process vga, cif, sif, qcif and qsif but has optimal performance with cif resolution (30 fps) and vga resolution (5 fps). the algorithm is philips proprietary. the compression ratio is continuously programmable by setting the maximum number of bits which can be used for 4 compressed lines, a so-called band (see table 1). it is possible to reduce the yuv input data by scaling down (divide by 2 or divide by 4 operations) to 7 or 6 bits per sample. for compression with an output rate below 2 bpp (bits per pixel) it leads to performance improvement. for a number of compression ratios, performance is also improved thanks to different quantization tables which are defined and stored in a rom. the required table must be selected via software. real time decoding can be done in software on any pentium ? platform. handbook, full pagewidth fce430 prefilter a prefilter b down scaler yuv7 to yuv0 to transfer buffer compression engine video_output_format pal_vga uv_exchange prefilter_a_on_off prefilter_b_on_off prefilter b_comb_on_off compression_mode vp_c_ bitcost_(msb/lsb) fig.3 the video formatter and compression engine. table 1 data rate performed by compression engine format advised data rate maximum data rate cif/sif 2 bpp 12 bpp (uncompressed) qcif/qsif 6 bpp uncompressed vga high quality 3 bpp 4 bpp vga 1.5 bpp 3 bpp raw vga high quality 4 bpp 4 bpp
2000 jan 27 13 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL 8.5 transfer buffer the transfer buffer module (see fig.4) takes care of a smooth transfer of the data to the fifo of the usb. moreover the transfer buffer can insert inband synchronization words in the video data stream. this function can be switched on and off with inband_control in register vp_tr_control (0x36). the synchronization words can only be used with non-compressed data stream and are formatted like 0x00 0xff 0x 7 9 . (subscript denotes the number of bits and the frame counter is circular incrementing). the non-compressed data is formatted like: 4:2:0: ...., 4:2:2: ...., where c denotes u-data in the even lines (0, 2, 4 etc.) and v-data in the odd lines (1, 3, 5 etc.). 8.6 usb video fifo the usb video fifo is programmed via the i 2 c-bus (see fig.5). the fifo is designed to achieve three different packets containing video on the isochronous usb channel. video data is contained in a chain of equally sized usb packets, except for the last packet of a video frame which is always smaller. the video frames can be separated from each other by one or more 0-length packets. for low frame rates (below 10 frames per second) there are always 0-length packets in the stream. the host can synchronize on the smaller packets for the high frame rates and on the 0-length packets for the low frame rates. for every mode the fifo must be adjusted. there are three parameters to program the video fifo: packet_size (0x06): this value indicates the length of all packets with video data except for the last packet of a video frame fifo_offset (0x04): this value indicates the number of data in the fifo before a new packet will be transmitted over usb read_spacing (0x07): this value indicates the number of 12 mhz clock cycles between read actions from the fifo. moreover the fifo is enabled and disabled with fifo_active (0x05). the write process to the fifo is controlled by the transfer buffer and not programmable. the read process is executed in the psie-mmu and is driven by the usb frame interval (1 ms). every frame interval the psie-mmu tries to read packet_size bytes from the fifo. this read process will not be started when a new video frame is stored in the fifo and there are less than fifo_offset bytes written. the read process stops if the next bytes are of another video frame, or if the read-pointer would overtake the write-pointer. read_spacing determines the read rate. its value can easily be determined with the formula: read_spacing 12000 packet_size ---------------------------------------- < handbook, full pagewidth write sync fifo ptr_to_start_vframe write read read enable data to psie-mmu fce431 data from transfer buffer fifo_offset read_spacing fifo_active packet_size fig.4 usb video fifo.
2000 jan 27 14 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL 8.7 psie-mmu, i 2 c-bus interface and usb ram space the programmable serial interface engine (psie) and memory management unit (mmu) is the heart of the usb protocol hardware (see fig.5). it formats the actual packets that are transferred to the usb and passes the incoming packets to the right end-point buffers. these buffers are allocated as part of the usb ram space. the microcontroller communicates via the i 2 c-bus with the psie-mmu. the i 2 c-bus protocol distinguishes three register spaces. these spaces are addressed via different commands. the command is sent to the command address. depending on the command it is sent to the psie-mmu and/or to the command interpreter which configures the (de-)mux to open the path to the right register space. subsequent write/reads to/from the data address store or retrieve data from the register space selected by the command. 8.8 atx interface the SAA8115HL contains an analog bus driver, called the atx. it incorporates a differential and two single-ended receivers and a differential transmitter. the interface to the bus consists of a differential data pair (atxdm and atxdp). handbook, full pagewidth pi_address + 0x pi_address + 10 to/from microcontroller i 2 c-bus interface command interpreter (de)mux to psie-mmu psie-mmu register space set mode register space non usb and video fifo registers fce432 fig.5 i 2 c-bus interface and register map. 8.9 audio the SAA8115HL contains a microphone supply and an amplifier circuit composed of two stages: a low noise amplifier (lna) and a variable gain amplifier. the lna has a fixed gain of 26 db while the variable gain amplifier can be programmed between 0 and 30 db by steps of 2 db. the gain control can be done via either the snert interface or the i 2 c-bus interface (see table 57). the serial interface must be first selected using bit sis (see table 57). the frequency transfer characteristic of the audio path must be controlled via external high-pass or low-pass filters. the pll converts the 48 mhz to 256f s (f s = audio sample frequency). there are three modes for the pll to achieve the sample frequencies of 48, 44.1 or 32 khz (see table 2). the bitstream adc samples the audio signal. it runs at an oversample rate of 256 times the base sample rate. in the application, the bitstream can be converted to parallel 16-bit samples. this conversion is programmable with respect to the effective sample frequency (dropping sample results in a lower effective sample frequency) and sample resolution. as a result the effective sample rate can be determined.
2000 jan 27 15 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL table 2 adc clock frequencies and sample frequencies note 1. not supported. 8.10 sensor pulse pattern generator the SAA8115HL incorporates a pulse pattern generator (ppg) function. the ppg can be used for medium resolution pal, cif and vga ccd-sensors (see table 3). depending on the sensor type, an external inverter driver should be required to convert the 3.3 v pulses into a voltage suitable for the used ccd-sensor. the active video size is 512 288 for medium resolution pal, 352 288 for cif and 640 480 for vga. the total h v size are 685 292 for medium resolution pal/cif and 823 486 for vga. it should be noted that additional hd pulses are added during the vertical blanking interval to reach a total of 312 lines in pal and cif modes and 525 lines in vga mode as required by the saa8112hl. a high level of flexibility is available for the ppg thanks to 19 internal registers (see section 9.1.3). clock (mhz) dividing number sample frequency (khz) adc clock (mhz) 8.1920 1 32 4.096 2 16 2.048 4 8 1.042 8 note 1 note 1 11.2996 1 44.1 5.6448 2 22.05 2.8224 4 11.025 1.4112 8 5.5125 0.7056 12.2880 1 48 6.144 2 24 3.072 4 12 1.536 8 6 0.768 table 3 typical SAA8115HL compatible sensors sensor type brand part number vga sony icx098ak panasonic mn3777pp and mn37771pt sharp lz24bp medium resolution pal sony icx054, icx086 and icx206 panasonic mn37210fp sharp lz2423b and lz2423h toshiba tcd5391ap cif sharp lz244d and lz2547 other sensors all the sensors fully compatible with the above mentioned sensors
2000 jan 27 16 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL 8.11 power management usb requires the device to switch power states. the SAA8115HL contains a power management module since the complete camera may not consume more than 500 m a during the power state called suspend. this requires that even the crystal oscillator must be switched off. the SAA8115HL is not functional except for some logic that enables the ic to wake-up the camera. after wake-up of the SAA8115HL first the clock to the microcontroller is generated and thereafter an interrupt is generated to wake-up the microcontroller. therefore the clock of the microcontroller is generated by the SAA8115HL. the power management module also sets a flag in register set_mode_and_read (psie_mmu_status). after a reset the microcontroller should check this register via the i 2 c-bus and find the cause of the wake-up. different causes may require different start-up routines. the internal video processing core uses another supply domain which can be switched off during suspend mode. the ppg is switched off by setting ppg_resume_mode (0x08) and resetting pal_vga (0x09). in non cif modes the power consumption is reduced by resetting compression_mode (0x2f) and compression_clock (0x09). the SAA8115HL has the feature to autonomously wake-up from suspend mode, but requires microcontroller interference before going in suspend mode (via the signal on pin suspreadynot). since the main oscillator of the SAA8115HL is switched off during suspend mode, precautions are needed to avoid undefined states when the clock is switched on. this is ensured via the pins clockon and trc. pin clockon goes high as soon as the main oscillator is switched on. the oscillator will need some time to make a stable 48 mhz signal. however, the clock is only passed through to other parts of the SAA8115HL when the level on pin trc reaches a certain threshold. the time needed to reach the threshold can be trimmed with an external rc circuit. 8.12 power supply a power supply regulator is integrated in the device. this dc-to-dc converter transforms the usb supply voltage (range from 4.0 to 5.5 v) into a stable 5 v supply voltage. this power domain is switchable. the power circuit also generates a reset signal when the external 3.3 v supply voltage is stable and in range.
2000 jan 27 17 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL 9 control register description this specification gives an overview of all registers. 9.1 snert (uart) the SAA8115HL is partly controlled via snert. the frame rate converter, the sdram interface, the video formatter, the compression engine, the ppg, the smp and the audio functions are controlled via snert. this snert interface works independently from the frame rate and can always be operated in the full frequency range. via snert the following registers are accessible (see table 4). table 4 snert write registers SAA8115HL 9.1.1 g eneral register table 5 detailed description of snert general register 0x00 address function 00 write register soft reset (see table 5) 01 to 05 write registers frame rate converter (frc) including the sdram interface 06 and 07 reserved 08 to 1a write registers pulse pattern generator (ppg) 1b to 1f reserved 20 to 38 write registers video formatter and compression engine 39 to 3c reserved 3d and 3e write registers switch mode power (smp) 3f write register audio variable gain ampli?er bit snert register 00: soft_reset 76543210 p arameter xxxxx reserved reset_vp_c 1 compression engine in reset state 0 compression engine operating reset_vp_vf 1 formatter engine in reset state 0 formatter engine operating reset_frc 1 frame rate converter engine in reset state (by default) 0 frame rate converter engine operating
2000 jan 27 18 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL 9.1.2 f rame rate converter and sdram interface registers table 6 detailed description of snert frc and sdram register 0x01 table 7 detailed description of snert frc and sdram register 0x02 bit snert register 01: frc_control_0 76543210 p arameter x reserved x x x number of active lines after rising edge of vs signal; range: 0 to 6 (by default 0) framerate_divider_select_bit 1 1 1 undefined 1 1 0 32 (30 fps in; 0.9375 fps out) 1 0 1 16 (15 fps in; 0.9375 fps out) 1 0 0 6 (30 fps in; 5 fps out) 0 1 1 3 (30 fps in; 10 fps out) or (15 fps in; 5 fps out) 0 1 0 2 (30 fps in; 15 fps out) or (15 fps in; 7.5 fps out) 0 0 1 1 (1 fps in; 1 fps out) (by default) 0 0 0 undefined llc_clkfreq 1 24 mhz (by default) 0 12 mhz bit snert register 02: frc_control_1 76543210 p arameter x x x reserved refresh_mode 1 automatic sram refresh 0 precharge command as implicit refresh (by default) refresh_clock (msbs) x x see table 9 input_format 1 1 undefined 1 0 medium resolution 0 1 cif 0 0 vga (by default)
2000 jan 27 19 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL table 8 detailed description of snert frc and sdram register 0x03 table 9 detailed description of snert frc and sdram register 0x04 table 10 detailed description of snert frc and sdram register 0x05 bit snert register 03: frc_rowwidth 76543210 p arameter xxxxxxxx speci?es the width of the row of the sdram 95 for pal sensors 159 for vga sensors (by default) 63 for cif sensors bit snert register 04: frc_refresh_lsb 76543210 p arameter xxxxxxxx speci?es the number of clock cycles between two refresh cycles 246 for pal sensors 395 for vga sensors (by default) 239 for cif sensors bit snert register 05: frc_stopwrite 76543210 p arameter xxxxxxxxn umber of lines in a frame 243 for vga sensors (by default) 146 for pal or cif sensors
2000 jan 27 20 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL 9.1.3 p ulse pattern generator registers table 11 detailed description of snert ppg register 0x08 bit snert register 08: ppg_control_0 76543210 p arameter x x x reserved shutter_update_buffer 1 during the vertical blanking (shutter speed is buffered) 0 immediately (by default) ppg_resume_mode 1 switched off (except vertical transfer pulses in case of vga sensors) 0 operating (by default) ppg _framerate 1 1 x undefined 101 5fps 1 0 0 10 fps 0 1 1 15 fps 0 1 0 20 fps 0 0 1 24 fps 0 0 1 30 fps (by default)
2000 jan 27 21 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL table 12 detailed description of snert ppg register 0x09 bit snert register 09: ppg_control_1 76543210 p arameter x reserved compression_clock 1 1 x x reserved 1011 24mhz 1010 19.2 mhz 1001 16mhz 1000 12 mhz (by default) 0111 9.6mhz 0110 8.0mhz 0101 6.0mhz 0100 4.8mhz 0011 4.0mhz 0010 2.4mhz 0001 2.0mhz 0000 off vga_sensor_type (valid if msb set to logic 0) 1 1 vga (sony and panasonic) 1 0 vga (sharp) 0 x reserved pal_vga 1 pal or cif timing 0 vga timing (by default)
2000 jan 27 22 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL table 13 detailed description of snert ppg register 0x0a note 1. if bits [5 to 3] equal bits [2 to 0] then fh2 is the inverse of fh1. bit snert register 0a: ppg_h_ctrl 76543210 p arameter x reserved rg_short 1 rg pulse width is set to half of nominal value 0 rg pulse width is set to nominal value fh2_ctrl (non ft mode); note 1 1 x 1 no horizontal blanking 1 x 0 no horizontal blanking, pulse inverted 0 1 1 blanked to high, starts high 0 1 0 blanked to low, starts low 0 0 1 blanked to low, starts high 0 0 0 blanked to high, starts low fh1_ctrl (non ft mode); note 1 1 x 1 no horizontal blanking, pulse inverted 1 x 0 no horizontal blanking 0 1 1 blanked to high, starts low 0 1 0 blanked to high, starts high 0 0 1 blanked to high, starts low 0 0 0 blanked to low, starts high
2000 jan 27 23 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL table 14 detailed description of snert ppg register 0x0b bit snert register 0b: ppg_v_inv 76543210 p arameter a4_inv 1 positive pulses 0 negative pulses a3_inv 1 positive pulses 0 negative pulses a2_inv 1 negative pulses 0 positive pulses a1_inv 1 negative pulses 0 positive pulses b4_inv 1 positive pulses 0 negative pulses b3_inv 1 positive pulses 0 negative pulses b2_inv 1 negative pulses 0 positive pulses b1_inv 1 negative pulses 0 positive pulses
2000 jan 27 24 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL table 15 detailed description of snert ppg register 0x0c bit snert register 0c: ppg_h_inv 76543210 p arameter clk2_inv 1 inverted pulses 0 nominal pulses clk1_inv 1 inverted pulses 0 nominal pulses fs_inv 1 positive pulses 0 negative pulses fcds_inv 1 positive pulses 0 negative pulses fr_inv 1 positive pulses 0 negative pulses c3_inv 1 negative pulses 0 positive pulses c2_inv 1 negative pulses 0 positive pulses c1_inv 1 negative pulses 0 positive pulses
2000 jan 27 25 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL table 16 detailed description of snert ppg register 0x0d table 17 detailed description of snert ppg register 0x0e table 18 detailed description of snert ppg register 0x0f bit snert register 0d: ppg_misc_inv 76543210 p arameter select_a2 1 a2 is high during read-out gate in line 2 0 a2 is low during read-out gate in line 2 select_a3 1 a3 equals a4 (in case of vga type 1 sensors) 0 a3 equals a2 c4_inv 1 negative pulses 0 positive pulses cr_inv 1 positive pulses 0 negative pulses bcp_inv 1 negative pulses 0 positive pulses dcp_inv 1 negative pulses 0 positive pulses hd_inv 1 negative pulses 0 positive pulses vd_inv 1 negative pulses 0 positive pulses bit snert register 0e: ppg_shutterspeed_v_lsb 76543210 p arameter xxxxxxxx8 lsbs of line number (9 bits) bit snert register 0f: ppg_shutterspeed_h_lsb 76543210 p arameter xxxxxxxx8 lsbs of pixel number (10 bits)
2000 jan 27 26 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL table 19 detailed description of snert ppg register 0x10 table 20 detailed description of snert ppg register 0x11 table 21 detailed description of snert ppg register 0x12 table 22 detailed description of snert ppg register 0x13 table 23 detailed description of snert ppg register 0x14 table 24 detailed description of snert ppg register 0x15 bit snert register 10: ppg_shutterspeed_msb 76543210 p arameter xxxx reserved sensor_type 1 sony 0 sharp x x msbs of pixel number (10 bits) x msbs of line number (9 bits) bit snert register 11: ppg_bcp_start_lsb 76543210 p arameter xxxxxxxx8 lsbs of pixel number (10 bits) where bcp starts bit snert register 12: ppg_bcp_stop_lsb 76543210 p arameter xxxxxxxx8 lsbs of pixel number (10 bits) where bcp stops bit snert register 13: ppg_dcp_start_lsb 76543210 p arameter xxxxxxxx8 lsbs of pixel number (10 bits) where dcp starts bit snert register 14: ppg_dcp_stop_lsb 76543210 p arameter xxxxxxxx8 lsbs of pixel number (10 bits) where dcp stops bit snert register 15: ppg_bcp_dcp_msb 76543210 p arameter x x msbs of ppg_dcp_stop x x msbs of ppg_dcp_start x x msbs of ppg_bcp_stop x x msbs of ppg_bcp_start
2000 jan 27 27 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL table 25 detailed description of snert ppg register 0x16 table 26 detailed description of snert ppg register 0x17 table 27 detailed description of snert ppg register 0x18 table 28 detailed description of snert ppg register 0x19 table 29 detailed description of snert ppg register 0x1a bit snert register 16: ppg_b3_start_lsb 76543210 p arameter xxxxxxxx8 lsbs of pixel number (10 bits) where b3 starts bit snert register 14: ppg_b3_stop_lsb 76543210 p arameter xxxxxxxx8 lsbs of pixel number (10 bits) where b3 stops bit snert register 18: ppg_b4_start_lsb 76543210 p arameter xxxxxxxx8 lsbs of pixel number (10 bits) where b4 starts bit snert register 19: ppg_b4_stop_lsb 76543210 p arameter xxxxxxxx8 lsbs of pixel number (10 bits) where b4 stops bit snert register 1a: ppg_b3_b4_msb 76543210 p arameter x x msbs of ppg_b4_stop x x msbs of ppg_b4_start x x msbs of ppg_b3_stop x x msbs of ppg_b3_start
2000 jan 27 28 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL 9.1.4 v ideo formatter and compression engine registers table 30 detailed description of snert video formatter register 0x20 bit snert register 20: vp_vf_contrl_0 76543210 p arameter x x reserved uv_exchange x exchange chrominance irregularities if needed scale_data: limits the number of bits of the video signal 1 1 undefined 1 0 6 bits 0 1 7 bits 0 0 8 bits prefilter_b_comb_on_off (if ?lter b is on) 1 pre?lter b_comb with 13 taps 0 pre?lter b_comb with 7 taps prefilter_b_on_off 1 on with 7 taps 0 bypassed prefilter_a_on_off 1 on with 3 taps 0 bypassed
2000 jan 27 29 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL table 31 detailed description of snert video formatter register 0x21 table 32 detailed description of snert video formatter register 0x22 table 33 detailed description of snert video formatter register 0x23 bit snert register 21: vp_vf_contrl_1 76543210 p arameter 420_fil_bypass: 4 :2:0 for matter mode 1 throw away samples 0 average uv samples vga_raw: data mode 1 raw data, no scaling or 4:2:0 formatting 0 yuv data video_output_format 1 1 1 undefined 110 sif 1 0 1 qsif 1 0 0 unde?ned 011 vga 010 cif 0 0 1 qcif 0 0 0 sub-qcif video_input_format 1 1 1 undefined 1 1 0 square sif (sensors with square pixels) 1 0 1 cif (sensors with 12/11 pixel ratio format) 1 0 0 medium resolution pal 0 1 1 unde?ned 0 1 0 unde?ned 0 0 1 unde?ned 000 vga bit snert register 22: vp_vf_vcoef_c0_0 76543210 p arameter x reserved xxxxxxxver tical ?lter coef?cient tap 0 phase 0 bit snert register 23: vp_vf_vcoef_c0_1 76543210 p arameter x reserved xxxxxxxver tical ?lter coef?cient tap 0 phase 1
2000 jan 27 30 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL table 34 detailed description of snert video formatter register 0x24 table 35 detailed description of snert video formatter register 0x25 table 36 detailed description of snert video formatter register 0x26 table 37 detailed description of snert video formatter register 0x27 table 38 detailed description of snert video formatter register 0x28 table 39 detailed description of snert video formatter register 0x29 bit snert register 24: vp_vf_vcoef_c0_2 76543210 p arameter x reserved xxxxxxxver tical ?lter coef?cient tap 0 phase 2 bit snert register 25: vp_vf_vcoef_c1_0 76543210 p arameter x reserved xxxxxxxver tical ?lter coef?cient tap 1 phase 0 bit snert register 26: vp_vf_vcoef_c1_1 76543210 p arameter x reserved xxxxxxxver tical ?lter coef?cient tap 1 phase 1 bit snert register 27: vp_vf_vcoef_c1_2 76543210 p arameter x reserved xxxxxxxver tical ?lter coef?cient tap 1 phase 2 bit snert register 28: vp_vf_vcoef_c2_0 76543210 p arameter x reserved xxxxxxxver tical ?lter coef?cient tap 2 phase 0 bit snert register 29: vp_vf_vcoef_c2_1 76543210 p arameter x reserved xxxxxxxver tical ?lter coef?cient tap 2 phase 1
2000 jan 27 31 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL table 40 detailed description of snert video formatter register 0x2a table 41 detailed description of snert video formatter register 0x2b table 42 detailed description of snert video formatter register 0x2c table 43 detailed description of snert video formatter register 0x2d table 44 detailed description of snert video formatter register 0x2e bit snert register 2a: vp_vf_vcoef_c2_2 76543210 p arameter x reserved xxxxxxxver tical ?lter coef?cient tap 2 phase 2 bit snert register 2b: vp_vf_vcoef_c3_0 76543210 p arameter x reserved xxxxxxxver tical ?lter coef?cient tap 3 phase 0 bit snert register 2c: vp_vf_vcoef_c3_1 76543210 p arameter x reserved xxxxxxxver tical ?lter coef?cient tap 3 phase 1 bit snert register 2d: vp_vf_vcoef_c3_2 76543210 p arameter x reserved xxxxxxxver tical ?lter coef?cient tap 3 phase 2 bit snert register 2e: vp_vf_limiter 76543210 p arameter xxxxxxxx output of the video formatter is clipped to this maximum value
2000 jan 27 32 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL table 45 detailed description of snert compression engine register 0x2f table 46 detailed description of snert compression engine register 0x30 table 47 detailed description of snert compression engine register 0x31 table 48 detailed description of snert compression engine register 0x32 table 49 detailed description of snert compression engine register 0x33 bit snert register 2f: vp_vf_control 76543210 p arameter x reserved qtable_select: quantization table select xxxx range [0 : 15] dc_coeff_length 1 1 undefined 1 0 8 bits 0 1 7 bits 0 0 6 bits compression_mode 1on 0 off (by default) bit snert register 30: vp_c_ymask 76543210 p arameter xxxxxxxx operates an and between this value and the compression engine input; can be used to set bit positions in the y signal to 0 (by default 0x00) bit snert register 31: vp_c_uvmask 76543210 p arameter xxxxxxxx operates an and between this value and the compression engine input; can be used to set bit positions in the uv signal to 0 (by default 0x00) bit snert register 32: vp_c_bitcost_msb 76543210 p arameter xxxxxxxx set the compression ratio; the bitcost determines the maximum number of bits generated by the compression algorithm for 4 subsequent lines bit snert register 33: vp_c_bitcost_lsb 76543210 p arameter xxxxxxxx set the compression ratio; the bitcost determines the maximum number of bits generated by the compression algorithm for 4 subsequent lines
2000 jan 27 33 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL table 50 detailed description of snert compression engine register 0x34 table 51 detailed description of snert compression engine register 0x35 table 52 detailed description of snert compression engine register 0x36 table 53 detailed description of snert compression engine register 0x37 table 54 detailed description of snert compression engine register 0x38 bit snert register 34: vp_c_threshold_msb 76543210 p arameter xxxxxxxx output of the video formatter is clipped to this maximum value bit snert register 35: vp_c_threshold_lsb 76543210 p arameter xxxxxxxx threshold must be set to: (number of uv blocks per band) (dc_coeff_length + 2) bit snert register 36: vp_tr_control 76543210 p arameter x reserved vga_format 1 4:2:2 (uncompressed only) 0 4:2:0 inband_control 1on 0 off llc_out_div: select the rate at which the video data is transmitted to the usb core xxxxx range [1 to 31] bit snert register 37: vp_tr_sqcif_offset 76543210 p arameter vertical_offset xxxx range 3 [0 to 15] horizontal_offset xxxx range 4 [0 to 12] bit snert register 38: vp_vs_v_shift 76543210 p arameter xxxxxxxx shift internal line counter with respect to vs pulse
2000 jan 27 34 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL 9.1.5 s witch mode power registers table 55 detailed description of snert smp register 0x3d table 56 detailed description of snert smp register 0x3e 9.1.6 a udio variable gain amplifier table 57 detailed description of snert audio gain ampli?er register 0x3f bit snert register 3d: smp_period 76543210 p arameter xxxxxxxxper iod of smp signal in units of 4 xosc_period (0 by default) bit snert register 3e: smp_lowtime 76543210 p arameter xxxxxxxxlow edge of smp signal in units of 4 xosc_period (0 by default) bit snert register 3f: audio_vgain 76543210 p arameter x x reserved sis: serial interface select 1 snert 0i 2 c-bus x reserved xxxxvariable gain settings (0 to 30 db)
2000 jan 27 35 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL 9.2 i 2 c-bus interface the usb function has its own i 2 c-bus interface for communication with the microcontroller. the i 2 c-bus uses two addresses: command address for writing commands to the memory manager (mm) data address for writing/reading data to/from the memory manager (mm). an address is a byte. the 7 msbs are the actual address, the lsb is the r/ w bit. when it is logic 0, data is transferred from the master to the slave, when it is logic 1, data is written from the slave to the master. the 6 msbs of the two addresses are equal and are defined by the pi_address = 010111 (see table 58). the lsb of the address differentiates between the command address and the data address. when bit 1 is logic 1 the address is the command address (0x5e) and when bit 1 is logic 0 the address is one of the data addresses (0x5c or 0x5d). table 58 i 2 c-bus addresses 9.2.1 c ommands the commands listed in table 59 must be sent to the i 2 c-bus address 0x5e. table 59 i 2 c-bus usb command codes bit address 76543210 01011100 0x5c: for writing data to the memory manager 01011101 0x5d: for reading data from the memory manager 01011110 0x5e: for writing commands 01011111 0x5f: not in use bit function 76543210 0 0 end-point number select end-point 0 1 end-point number read/write status 1 0 end-point number initialize/read status information 1101 address read/write register bank 11100xxx not used 11101000 set non-usb register 11110000 read/write data 11110001ackno wledge setup 11110010 set buffer empty 11111010 set buffer full 11110100 read interrupt register 11110101 read current frame number 11110110 send resume 11110111 set status change bits 11110011 set mode
2000 jan 27 36 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL table 60 detailed description of set mode and write register overview table 61 detailed description of set mode and write byte 3 byte set_mode_and_write 3 n1 timer: programmable timer for power management; counts 12 mhz cycles; must be bigger than number of cycles needed for the microcontroller to go in power-down state after pin suspreadynot is made low 2 n2 timer: programmable timer for power management; counts 12 mhz cycles; determines the time between the microcontroller clock is switched off and the main clock is switched off 1 psie-mmu control byte (see table 61) bit psie-mmu control byte 76543210 p arameter x x x reserved interrupt after isochronous audio transfer 1 for each isochronous audio transfer an interrupt to the microcontroller will be generated; default set to logic 1 upon general power-on reset and/or bus reset by the SAA8115HL 0 no interrupts are given to the microcontroller interrupt after isochronous video transfer 1 for each isochronous video transfer an interrupt to the microcontroller will be generated; default set to logic 1 upon general power-on reset and/or bus reset by the SAA8115HL 0 no interrupts are given to the microcontroller audio end-point 1 audio end-point enabled; default set to logic 1 upon general power-on reset and/or bus reset by the SAA8115HL 0 audio end-point disabled; the psie-mmu will not react on in-tokens on the audio end-point video end-point 1 video end-point enabled; default set to logic 1 upon general power-on reset and/or bus reset by the SAA8115HL 0 video end-point disabled; the psie-mmu will not react on in-tokens on the video end-point error debug mode 1 interrupts are generated only in the event the transfer is not successfully completed; the microcontroller can read data from the interrupt and status registers to see the cause of this error 0 all successful usb transactions are reported to the microcontroller via an interrupt; default set to logic 0 upon general power-on reset by the SAA8115HL
2000 jan 27 37 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL table 62 detailed description of set mode and read status byte 9.2.2 e nd - points the SAA8115HL has 6 logical end-points which are listed in table 63. table 63 mapping of logical to physical end-point numbers for used end-points bit psie-mmu status byte 76543210 p arameter xxxx reserved remote wake-up status ?ag 1 remote wake-up when device is in suspend mode 0 no remote wake-up resume status ?ag 1 bus resume by the host when device is in suspend mode 0 no bus resume bus reset status ?ag 1 bus reset 0 no bus reset power-up status ?ag 1 general power-up reset 0 no power-up reset end-point name logical end-point buffer size physical end-point out in control end-point 0 8 0 1 control end-point 1 8 2 3 interrupt end-point 2 8 - 4 interrupt end-point 3 8 - 5 iso video end-point 4 96.0 - 6 iso video end-point 5 35.1 - 7
2000 jan 27 38 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL 9.2.3 c ontrol top registers the following registers can be written on i 2 c-bus address 1 after the command 0xe8 on i 2 c-bus address 0. table 64 i 2 c-bus control top registers table 65 detailed description of i 2 c-bus control top registers 0x08 address control top registers (base address: 0x08) 0x08 clock control 0x09 reset control 0x0a mux block control 0x0b power-on analog modules control bit top register 0x08: clkshop_control 76543210 p arameter select adc clock source 1 sel_ad: clock generated from adc 0 sel_pll: clock generated from pll set clock dividers for adc 0 0 set_divide00: divided by 1 0 1 set_divide01: divided by 2 1 0 set_divide10: divided by 4 1 1 set_divide11: divided by 8 x reserved disable 48 mhz clock 1 dis_clk_48: disable 48 mhz clock 0 enable clock disable receiver clock 1 dis_clk_rec: disable receiver clock 0 enable clock disable adc clock 1 dis_clk_ad: disable adc clock 0 enable clock x reserved
2000 jan 27 39 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL table 66 detailed description of i 2 c-bus control top registers 0x09 table 67 detailed description of i 2 c-bus control top registers 0x0a bit top register 0x09: rst_gen and pll_control 76543210 p arameter set pll frequency 0 0 fcode00: 256 44.1 khz 0 1 fcode01: 256 32 khz 1 0 fcode10: 256 48 khz 1 1 fcode11: 256 44.1 khz x x reserved reset psie-mmu top module 1 upc_rst_mmu: resetting the usb protocol block (called psie-mmu) during tests or in case of errors 0 no reset x reserved reset adif top module 1 upc_rst_adif: resetting the digital audio part during tests or in case of errors 0 no reset reset agc module 1 upc_rst_agc: resetting the agc control during tests or in case of errors 0 no reset bit top register 0x0a: io_mux_control 76543210 p arameter xxxxxxxx reserved
2000 jan 27 40 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL table 68 detailed description of i 2 c-bus control top registers 0x0b bit top register 0x0b: power_control_of_analog_modules 76543210 p arameter power control oscillator module 1 upc_osc_off: power management 48 mhz enabled 0 power management 48 mhz disabled power control audio module 1 upc_osc_ad_off: power management audio enabled 0 power management audio disabled power control pll module 1 upc_pll_off: pll power-off 0 power-on x reserved power control adc module left channel 1 upc_adl_off: power-off 0 power-on power control adc module right channel 1 upc_adr_off: power-off 0 power-on power control agc module left channel 1 upc_agcl_off: power-off 0 power-on power control agc module right channel 1 upc_agcr_off: power-off 0 power-on
2000 jan 27 41 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL 9.2.4 v ideo fifo registers table 69 i 2 c-bus video fifo registers overview table 70 detailed description of i 2 c-bus video fifo registers 0x04 table 71 detailed description of i 2 c-bus video fifo registers 0x05 address video fifo registers (base address: 0x04) 0x04 fifo offset (8 lsbs) 0x05 fifo active and fifo offset (3 msbs) 0x06 packet size (8 lsbs) 0x07 read spacing and packet size (2 msbs) bit fifo register 0x04: fifo_offset 76543210 p arameter fifo_offset xxxxxxxx mode_fifo_offset: sets the minimum contents of the fifo that has to be reached, before a new video frame will be put on the usb. this value can be set between 0 and 2047. total 11 bits with 8 lsbs in this register and 3 msbs in register 0x05. bit fifo register 0x05: fifo_active and fifo_offset 76543210 p arameter fifo_active 1 mode_active: fifo is active and the contents of the other mode registers should not be updated by the microcontroller (maledictive) 0 fifo not active xxxx reserved fifo_offset (msbs) x x x 3 msbs of the offset value; see also register 0x04
2000 jan 27 42 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL table 72 detailed description of i 2 c-bus video fifo registers 0x06 table 73 detailed description of i 2 c-bus video fifo registers 0x07 bit fifo register 0x06: packet_size 76543210 p arameter packet_size xxxxxxxx mode_packet_size: sets the packet size of the usb video channel. packets can vary in size between 0 and 1023. total 10 bits with 8 lsbs in this register and 2 msbs in register 0x07. bit fifo register 0x07: read_spacing and packet_size 76543210 p arameter read_spacing xxxxxx mode_read_spacing: sets the periodicity of the read pulses; the periodicity can be set from 1 to 63 (from 000001 to 111111) packet_size x x mode_packet_size: 2 msbs of the value (8 lsbs in register 0x06)
2000 jan 27 43 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL 9.2.5 adif top registers table 74 i 2 c-bus adif top registers overview table 75 detailed description of i 2 c-bus adif top registers 0x0e address adif top registers (base address: 0x0c) 0x0c reserved 0x0d reserved 0x0e vga control gain 0x0f adif control (adif2mmu) bit adif register 0x0e: gain_control 76543210 p arameter x reserved gain_source_select 0 reserved 1 gain is controlled directly by bits 3 to 0 x x reserved gain_control; 0 to 30 db in steps of 2 db 0000 0db 0001 2db :::: : 0111 28db 1111 30db
2000 jan 27 44 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL table 76 detailed description of i 2 c-bus adif top registers 0x0f bit adif register 0x0f: adif_control 76543210 p arameter x reserved number of bytes per sample 0 0 0 (reserved) 0 1 1 (8 bits audio samples) 1 0 2 (16 bits audio samples) 1 1 3 (24 bits audio samples) selection mono/stereo operation 0 mono 1 stereo selection input for adc path (adif mux) 0 digital input (from i 2 s-bus) 1 analog input (from vin_left and vin_right) selection high-pass ?lter (dc ?lter) for adc down sample ?lter 0 high-pass filter off 1 high-pass filter on selection audio serial input format 00 i 2 s-bus 0 1 lsb-justified, 16 bits 1 0 lsb-justified, 18 bits 1 1 lsb-justified, 20 bits
2000 jan 27 45 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL 10 limiting values in accordance with the absolute maximum rating system (iec 60134). note 1. this concerns pins vbus1 and vbus2. 11 thermal characteristics 12 characteristics v ddd =v dda = 3.3 v 10%; t amb =0to70 c . symbol parameter conditions min. max. unit v dda analog supply voltage - 0.5 +4.0 v v dda_usb analog supply voltage from usb note 1 - 0.5 +5.5 v v ddd digital supply voltage - 0.5 +4.0 v v n voltage on pins agnd and dgnd - 0.5 +4.0 v all other pins - 0.5 v dd + 0.5 v t stg storage temperature - 55 +150 c t amb ambient temperature 0 70 c t j junction temperature - 40 +125 c symbol parameter conditions value unit r th(j-a) thermal resistance from junction to ambient in free air 45 k/w symbol parameter conditions min. typ. max. unit supplies v dddn digital supply voltage 3.0 3.3 3.6 v v ddan analog supply voltage 3.0 3.3 3.6 v v dda_usb analog supply voltage from usb note 1 4.0 5.0 5.5 v v dgnd digital ground supply - 0.3 0.0 +0.3 v v agnd analog ground supply - 0.3 0.0 +0.3 v i dddn digital supply current t amb =25 c -- tbf ma i ddan analog supply current t amb =25 c -- tbf ma data and control inputs v il low-level input voltage -- 0.8 v v ih high-level input voltage 2.0 -- v data and control outputs v ol low-level output voltage 0 - 0.1v ddd v v oh high-level output voltage 0.9v ddd - v ddd v
2000 jan 27 46 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL microphone supply i dd0 supply current - 0.85 1.2 ma v ref input reference voltage at 1 2 v dda - 1.65 - v v o output voltage v dda = 3.3 v - 3.0 - v i o output current -- 2.0 ma low noise ampli?er transfer function r i input impedance 3.5 5.0 - k w i dd1 supply current - 0.85 1.2 ma a ampli?cation 27 28 29 db v o(rms) output voltage (rms value) -- 800 mv thd total harmonic distortion note 2 -- 69 - 63 db v oo1 output offset voltage - 0.0 1.0 mv b iasing i ref1 reference current - 10 -m a variable gain ampli?er transfer function r i input impedance 7.0 10.5 13 k w i dd2 supply current - 0.45 0.6 ma a ampli?cation 0.0 - 32 db thd total harmonic distortion note 3 -- 88 - 82 db note 4 -- 65 - 57 db v oo2 output offset voltage a = 0 db - 1.0 2.0 mv a = 30 db - 14 30 mv b iasing i ref2 reference current - 10 -m a audio pll f i(clk) clock input frequency - 48 - mhz f o(clk) clock output frequency note 5 - 11.2996 - mhz b bandwidth - 2.3 - khz z damping - 0.98 - audio adc ( ?d converter) i nputs f i input signal frequency 1 - 20 khz v i(rms) input voltage (rms value) - 800 - mv t ransfer f unction n order of the ?d - 3 - n bit number of output bits - 1 - symbol parameter conditions min. typ. max. unit
2000 jan 27 47 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL n bit(eq) equivalent output resolution (bit) - 16 - dr i dynamic range at input note 6 - 96.6 - db f clk clock frequency -- 5.6448 mhz d clock frequency duty factor - 50 - % thd total harmonic distortion -- 70 - 55 db atx transceiver d river characteristics in full speed mode : pins atxdp and atxdm f o(sample) sample output frequency 4 - 48 khz t r rise transition time c l =50pf 4 - 20 ns t f fall transition time c l =50pf 4 - 20 ns t match transition time matching note 7 90 - 110 % v cr output signal crossover voltage 1.3 - 2.0 v z o driver output impedance steady state drive 30 - 42 w r eceiver characteristics in full speed mode : pins atxdp and atxdm f i(sample) sample input frequency 5 - 55 khz f i(d) data input frequency rate - 12.00 - mbits/s t frame frame interval - 1.000 - ms dc-to-dc converter 5v up and down converter ( switchable supply domain ) v o output voltage 4.9 5.0 5.1 v v ripple ripple on output voltage - 20 - mv i l load current -- 150 ma r dson_p1 pmos switch-on resistance; down converter note 8 - 1.0 -w r dson_n1 nmos switch-on resistance; down converter note 8 - 4.5 -w r dson_p2 pmos switch-on resistance; up converter note 8 - 1.1 -w r dson_n2 nmos switch-on resistance; up converter note 8 - 4.6 -w symbol parameter conditions min. typ. max. unit
2000 jan 27 48 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL notes 1. this concerns pins vbus1 and vbus2. 2. the distortion is measured at 1 khz, v o(rms) = 600 mv. 3. the distortion is measured at 1 khz, v o(rms) = 600 mv and a=0db. 4. the distortion is measured at 1 khz, v o(rms) = 600 mv and a = 30 db. 5. frequencies depend on pll settings (see table 2). 6. defined here as: 7. transition time matching: 8. including metal and contact resistance on chip and bonding wire resistance. 20 input voltage equivalent input noise voltage ------------------------------------------------------------------------------ - log t match t r t f -- - 100% =
2000 jan 27 49 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL 13 timing v ddd =v dda = 3.3 v 10%; t amb =0to70 c. note 1. c l = 11 pf; t amb =25 c. symbol parameter conditions min. typ. max. unit data input related to llc (see fig.6) p ins yuv0 to yuv7, href, vs t su(i)(d) data input set-up time 5 -- ns t h(i)(d) data input hold time 3 -- ns ppg high-speed pulses for sony icx098ak vga ccd-sensor (see fig.7) t d1 delay between falling edge c2 and rising edge c1 - 3.5 - 2.5 - 1.5 ns t d2 delay between rising edge c2 and falling edge c1 0 1.5 3 ns t d3 delay between falling edge c1 and rising edge fcds 20.5 21.5 22.5 ns t d4 delay between rising edge c1 and rising edge fs 21.5 22.5 23.5 ns t d5 delay between rising edge c1 and falling edge rg 0 1.5 3 ns t d6 delay between falling edge clk1 and rising edge c1 0 0.5 2 ns t d7 delay between rising edge clk1 and falling edge c1 2.5 3.0 3.5 ns t d8 delay between rising edge clk2 and rising edge c1 1 1.5 2 ns t wh(c1) c1 pulse width high 80 81 - ns t wl(c2) c2 pulse width low 84 85 - ns t wl(fcds) fcds pulse width low 17 18.5 - ns t wl(fs) fs pulse width low 41 42 - ns t wl(rg) rg pulse width low 42 43 - ns t wl(clk1) clk1 pulse width low 84 84.5 - ns t wh(clk2) clk2 pulse width high 39 40 - ns t r rise time note 1 pulse c1 - 4 - ns pulse c2 - 4 - ns pulse rg - 4 - ns pulse fcds - 4 - ns pulse fs - 4 - ns t f fall time note 1 pulse c1 - 4 - ns pulse c2 - 4 - ns pulse rg - 4 - ns pulse fcds - 4 - ns pulse fs - 4 - ns
2000 jan 27 50 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL handbook, full pagewidth fce606 t h(i)d t su(i)d llc data input fig.6 data input timing. handbook, full pagewidth fce607 50% 50% t d1 t d2 t wl(c2) t wl(clk1) t wh(c1) 50% 50% t wl(fcds) t d3 50% 50% 50% c1 c2 fcds t wl(fs) t d4 50% 50% fs t d5 t wl(rg) 50% 50% rg t d6 t d7 50% 50% t wh(clk2) t d8 50% 50% clk1 clk2 fig.7 ppg high-speed pulses for sony icx098ak vga ccd-sensor.
2000 jan 27 51 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL this text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader .this text is here in _ white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader.this text is here inthis text is here in white to force landscape pages to be rotated correctly when browsing through the pdf in the acrobat reader. white to force landscape pages to be ... 14 application information a ndbook, full pagewidth fce464 yuv7 to yuv0 vs href llc m smp reset vd hd snres sncl snda clk1 clk2 sdata ccd9 to ccd0 sclk strobe data7 to data0 ale ad10 to ad8 ad15 to ad11 dq15 to dq0 dqm csb ad10 to ad0 rasb casb web clken scl sda saa8112hl dsp and microcontroller SAA8115HL usb interface ucpor suspreadynot ucint suspend ucm clockon trc smp epprom (optional) sdram (optional) scle sdae eeprom tda878x sensor v-driver psen ucclk fs, fcds, dcp, bcp, clk1 c1 to c4, cr, rg a1 to a4, b1 to b4 fig.8 typical usb camera application.
2000 jan 27 52 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL 15 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p z y w v q references outline version european projection issue date iec jedec eiaj mm 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 20.1 19.9 0.50 22.15 21.85 1.40 1.10 7 0 o o 0.08 0.2 0.08 1.0 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot486-1 136e23 ms-026 99-12-03 00-01-19 d (1) (1) (1) 20.1 19.9 h d 22.15 21.85 e z 1.40 1.10 d 0 5 10 mm scale b p e q e a 1 a l p detail x l (a ) 3 b c b p e h a 2 d h v m b d z d a z e e v m a x y w m w m a max. 1.6 lqfp144: plastic low profile quad flat package; 144 leads; body 20 x 20 x 1.4 mm sot486-1 108 109 pin 1 index 73 72 37 1 144 36
2000 jan 27 53 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL 16 soldering 16.1 introduction to soldering surface mount packages this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our data handbook ic26; integrated circuit packages (document order number 9398 652 90011). there is no soldering method that is ideal for all surface mount ic packages. wave soldering is not always suitable for surface mount ics, or for printed-circuit boards with high population densities. in these situations reflow soldering is often used. 16.2 re?ow soldering reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. typical reflow peak temperatures range from 215 to 250 c. the top-surface temperature of the packages should preferable be kept below 230 c. 16.3 wave soldering conventional single wave soldering is not recommended for surface mount devices (smds) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. to overcome these problems the double-wave soldering method was specifically developed. if wave soldering is used the following conditions must be observed for optimal results: use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. for packages with leads on two sides and a pitch (e): C larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; C smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves at the downstream end. for packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. the footprint must incorporate solder thieves downstream and at the side corners. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 16.4 manual soldering fix the component by first soldering two diagonally-opposite end leads. use a low voltage (24 v or less) soldering iron applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
2000 jan 27 54 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL 16.5 suitability of surface mount ic packages for wave and re?ow soldering methods notes 1. all surface mount (smd) packages are moisture sensitive. depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). for details, refer to the drypack information in the data handbook ic26; integrated circuit packages; section: packing methods . 2. these packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink (at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version). 3. if wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. the package footprint must incorporate solder thieves downstream and at the side corners. 4. wave soldering is only suitable for lqfp, tqfp and qfp packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 5. wave soldering is only suitable for ssop and tssop packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. package soldering method wave reflow (1) bga, sqfp not suitable suitable hlqfp, hsqfp, hsop, htssop, sms not suitable (2) suitable plcc (3) , so, soj suitable suitable lqfp, qfp, tqfp not recommended (3)(4) suitable ssop, tssop, vso not recommended (5) suitable
2000 jan 27 55 philips semiconductors preliminary speci?cation digital camera usb interface SAA8115HL 17 definitions 18 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 19 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
? philips electronics n.v. sca all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owne r. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not con vey nor imply any license under patent- or other industrial or intellectual property rights. internet: http://www.semiconductors.philips.com 2000 69 philips semiconductors C a worldwide company for all other countries apply to: philips semiconductors, international marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 3 figtree drive, homebush, nsw 2140, tel. +61 2 9704 8141, fax. +61 2 9704 8139 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101 1248, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 20 0733, fax. +375 172 20 0773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 68 9211, fax. +359 2 68 9102 canada: philips semiconductors/components, tel. +1 800 234 7381, fax. +1 800 943 0087 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: sydhavnsgade 23, 1780 copenhagen v, tel. +45 33 29 3333, fax. +45 33 29 3905 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615 800, fax. +358 9 6158 0920 france: 51 rue carnot, bp317, 92156 suresnes cedex, tel. +33 1 4099 6161, fax. +33 1 4099 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 2353 60, fax. +49 40 2353 6300 hungary: see austria india: philips india ltd, band box building, 2nd floor, 254-d, dr. annie besant road, worli, mumbai 400 025, tel. +91 22 493 8541, fax. +91 22 493 0966 indonesia: pt philips development corporation, semiconductors division, gedung philips, jl. buncit raya kav.99-100, jakarta 12510, tel. +62 21 794 0040 ext. 2501, fax. +62 21 794 0080 ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, via casati, 23 - 20052 monza (mi), tel. +39 039 203 6838, fax +39 039 203 6800 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108-8507, tel. +81 3 3740 5130, fax. +81 3 3740 5057 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381, fax +9-5 800 943 0087 middle east: see italy netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 pakistan: see singapore philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland : al.jerozolimskie 195 b, 02-222 warsaw, tel. +48 22 5710 000, fax. +48 22 5710 001 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 319762, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 58088 newville 2114, tel. +27 11 471 5401, fax. +27 11 471 5398 south america: al. vicente pinzon, 173, 6th floor, 04547-130 s?o paulo, sp, brazil, tel. +55 11 821 2333, fax. +55 11 821 2382 spain: balmes 22, 08007 barcelona, tel. +34 93 301 6312, fax. +34 93 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 5985 2000, fax. +46 8 5985 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2741 fax. +41 1 488 3263 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2886, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: yukari dudullu, org. san. blg., 2.cad. nr. 28 81260 umraniye, istanbul, tel. +90 216 522 1500, fax. +90 216 522 1813 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 208 730 5000, fax. +44 208 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381, fax. +1 800 943 0087 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 3341 299, fax.+381 11 3342 553 printed in the netherlands 753505/03/pp 56 date of release: 2000 jan 27 document order number: 9397 750 06568

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